At the SFU Satellite Design Team, we’re building a CubeSat from scratch. One of my main roles is designing the onboard computer hardware, as well as developing a lot of the onboard software. This post is a brief overview of the two boards that I designed and the team have assembled thus far.

Both of these boards were designed and laid out by me using KiCad. The repositories for the board files can be found here.

OBC Prototype Rev. A

This board was completed in August, 2017. The design process began about 3 months before the prototype was assembled. It is a prototype of the entire computing system, including the following features:

  • Real time clock with built-in capacitor backup
  • Triple redundant nonvolatile memory (flash)
  • External watchdog timer
  • Single event latchup protection
  • TMS570LS0714 microcontroller
  • FTDI USB-UART converter
  • PC-104 form factor
  • Onboard voltage regulation

OBC Revision A OBC Revision A

This board will be used by the team to develop the flight software, as it represents a good approximation of the final flight hardware, and includes all of the core features. Crucial to this purpose is the inclusion of the JTAG header and FTDI adapter, meaning that only a standalone debugger is required to debug/program the device. Power and UART out can come over the integrated USB port.

Unfortunately, a couple of layout errors were discovered. The resistors surrounding the oscillator are slightly too close, and the edge of the JTAG connector covers one set of pin headers, used to enable and disable the watchdog.

Further testing of the board is underway at the time of this writing. Currently, we’re working to diagnose some JTAG connection issues regarding software support for the chip.

A key design decision made with this board was to make most functionality modular, in case something else doesn’t work. It is possible to enable and disable most of the auxiliary features such as the watchdog and SEL monitor. This helps isolate errors, and was important in diagnosing the JTAG issue, as it allowed us to ensure that the chip had no power or reset problems.

Additionally, communication headers for all peripheral devices are provided, allowing for easy logic analyzer connection, and the ability to interface peripherals with existing development boards that are used by the team.


Since the team’s development happens in separate sub teams, we have adopted a set of standards to ensure our hardware will all work together. Our form factor standard is PC-104, which just happens to fit inside a CubeSat. The standard defines the PCB size and connector layout, as well as the pinout of the connector. We have elected not to follow the standard pinout, but have instead created our own which is more modern and suited to our project.

PC-104 Stacked OBCs PC-104 Stacked OBCs

OBC Demo Board

The demo board came first in the lineage of SFUSat computing hardware. Designed and assembled in May and June of 2017, it served as a test platform for the MCU external peripherals and our more custom circuitry. Its peripherals were connected to the TMS570LS03x-04x LaunchPad, which has served as our development platform so far. The demo board has the following features:

Prototype of SEL protection circuitry with external load connector Watchdog chip with all important pins broken out Real time clock and capacitor backup Triple redundant nonvolatile memory The testing regime for this board included verification of the SEL mitigation circuitry. Based on the INA301, this circuit detects an over current condition and toggles the power supply accordingly. To test, power resistors were connected to simulate the load of the entire OBC. Then, the frequency of switching was measured. Under light current loads, DC was fed to the circuit. In an over current condition, the power supply was being toggled by the chip at around 60Hz, which matches the spec for chip response time. This meant that since the heavy load was never removed, the protection circuit was repeatedly toggling power to attempt to reset the system.

Demo board and rev A Demo board and OBC rev A

Issues uncovered using this board include an incorrect RTC footprint (hence the blue bodge wires), as the data sheet provided an unlabelled and improperly placed bottom view, instead of the standard footprint top view. However, the repair was successful and this board was used in development of the RTC driver software. Additionally, the flash memory onboard was EOL’d by the manufacturer shortly after we’d ordered it, so memory driver implementation was delayed.

The demo board was very helpful for the team’s design process, and will certainly be used in the future to bring members up to speed with peripheral driver development, and the overall architecture of the system. Since these boards were inexpensive to make, they are an excellent experimentation and learning platform for the higher risk scenarios, and they allow us to leverage a lot of the development hardware already acquired by the team.